Computational Storage Simulator & Custom Firmware
- JIT Compiler Engine: Engineered a highly optimized Just-In-Time compiler translating eBPF bytecode into native RV64IMA machine code, handling complex register mapping and isolated execution on bare-metal.
- Architectural Emulation: Overcame host PCIe bottlenecks by designing a RAM-backed NVMe simulator. Implemented asynchronous submission/completion ring buffers (SQ/CQ) via shared memory (`mmap`) between a Linux host and the RISC-V core.
- Hardware-Level Integration: Managed critical silicon constraints on the StarFive JH7110 SoC (VisionFive 2), including Memory-Mapped I/O (MMIO) and explicit L1/L2 Instruction-Cache coherency (flush/invalidate) for safe dynamic code execution.
- Hybrid Validation HAL: Developed a custom Hardware Abstraction Layer allowing seamless testing and debugging transition between x86-64 QEMU simulation and the physical RISC-V target.